1. Field of the Invention
This invention relates to the field of voltage controlled oscillators.
2. Background Art
In data recovery circuitry, digital data may be provided as a serial stream of pulses occurring at a certain data frequency. The recovery circuitry must have the ability to lock on to this data frequency in order to extract the digital information in a synchronous manner. One way to accomplish this is to utilize a voltage controlled oscillator (VCO) in a phase lock loop.
A voltage controlled oscillator produces an output signal at a certain oscillation frequency. This oscillating output is then compared with the incoming data signal to determine phase and frequency differences between the two signals. This difference is converted into a control voltage that is provided to the voltage controlled oscillator to drive the output frequency either up or down to match the incoming data frequency. For optimized performance at higher frequencies, the VCO should have a linear frequency versus voltage transfer function. For circuitry designed in an all-CMOS process, prior art VCO's do not have an acceptable response at higher operating frequencies. A block diagram of an example VCO design is illustrated in FIG. 1.
A control voltage V.sub.IN (10) is provided to a ramping means (11). The ramping means is coupled to a comparator block (13), which is in turn coupled to a latch (15). The latch provides the oscillating output to the ramping means (11) and to the phase lock loop.
The ramping means 11 provides a first ramping voltage signal to comparator block 13. The ramping voltage falls (or rises) until a signal on line 16, the oscillating output, triggers a reset of that ramping signal. At this point, a second ramping signal begins. When the second ramping signal is reset by the oscillating output, the first ramping signal begins falling (or rising) again. In comparator block 13, a comparator is used as threshold crossing detector. When the comparator detects that the ramping voltage provided from ramping means 11 has crossed a threshold voltage, the comparator block 13 provides a pulse to latch 15 to change the state of the latch. The state of the latch then provides the oscillating output F.sub.OUT on line 16 to the phase lock loop circuit and to the ramping means to control the switching of the ramping signals.
The time it takes for the ramping signals within the ramping means 11 to fall (or rise) from their original position to the threshold voltage, is the ideal time of the VCO half cycle, T.sub.H, where the half cycle is designed to be inversely proportional to the control voltage VN. Thus the ideal frequency function is given by: ##EQU1##
However, the ramping means does not switch the ramping voltage until latch 15 has changed states. Therefore, once the ramping voltage has crossed the threshold voltage, the comparator must detect the crossing and the latch must change states before the actual half cycle is completed. Thus an inherent delay caused by the comparator and the latch is introduced into the frequency function of the VCO. Therefore the actual half cycle of the VCO is T.sub.H' =T.sub.H +delv, where delv is the comparator/latch delay. The frequency function of the circuit becomes: ##EQU2##
This delay term causes a nonlinearity in the transfer function of the circuit as frequencies rise to the level at which the ideal half cycle is of the same order of magnitude as the delay term. In an all CMOS VCO, this delay can be significant. Therefore, the frequency versus voltage transfer function of the VCO, and consequently the phase locking ability of the phase lock loop, is unacceptable for use in some applications.
FIG. 2 illustrates the frequency versus voltage characteristics of an ideal VCO and the VCO of FIG. 1. As shown, the ideal frequency response is represented by the solid line with a slope of 1/(2 T.sub.H). The actual frequency response is represented by the dashed line which flattens out towards a frequency limit of 1/(2 delv). Thus the useable frequency range of the actual VCO is reduced.
A prior art voltage-controlled oscillator with a compensation loop is shown in FIG. 3. This circuit is disclosed in the article, "A 30 MHz Low-Jitter, High-Linearity CMOS Voltage-Controlled Oscillator", by Wakayama and Abidi in the IEEE Journal of Solid State Electronics, Vol. SC-22, No. 6, December, 1987, pgs. 1074-1080.
Transconductance (GM) converter 101 receives control voltage input signal 100 and outputs control current signals 130 and 113. Control current 130 is provided to VCO core block 102. VCO core 102 is coupled through ramp node 117 to capacitor 114 (C.sub.V), level shifter 103 and the negative input of comparator 105. VCO core 102 is also coupled through ramping node 118 to capacitor 114, level shifter 104 and the negative input of comparator 106. Level shifter 103 is coupled through line 119 to the positive input of comparator 106. Level shifter 104 is coupled through line 120 to the positive input of comparator 105. The output 121 of comparator 105 is coupled to the "set" input of latch 107. The output 122 of comparator 106 is coupled to the "reset" input of latch 107. The "Q" output of latch 107 provides clock output 115 (clk+), which is fed back to VCO core 102. The "Q*" output of latch 107 provides the inverted clock output 116 (clk-), which is also fed back to VCO core 102. The standard VCO block of this circuit comprises VCO core 102, level shifters 103 and 104, comparators 105 and 106, and latch 107.
The compensation loop for this prior art circuit comprises the divide-by-four circuit 108, clock generator circuit 109, frequency/voltage converter block 110 and difference amplifier 111. The divide-by-four circuit 108 is coupled to clock output 115 and inverted clock output 116 and also to clock generator 109. Clock generator 109 provides multi-phase clock signals through bus 123 to frequency/voltage converter 110. Frequency/voltage converter 110 receives current control signal 113 from transconductance converter 101 and provides a voltage signal 126 to the negative input of difference amplifier 111 and capacitor 112 (Chold). A bandgap reference voltage is provided to the positive input of the difference amplifier. The output of difference amplifier 111 is provided to node 125 which is also coupled to capacitor 112 and level shifters 103 and 104.
Transconductance converter 101 is responsible for driving the VCO core of this oscillator. Ideally, the transconductance converter satisfies the equation: EQU I(t)=gmV.sub.IN (t) (equation 3)
where gm is the transconductance value of block 101. Thus, a change in input voltage brings about a proportional change in output current.
The VCO core block 102 is constructed such that one output node has a low impedance path to a positive voltage supply while the other output node is discharging floating capacitor 114, C.sub.V, at a rate defined by control current 130. The inverted and non-inverted clock signals, 116 and 115, are responsible for switching the circuit so that the output nodes alternate between the conditions described. Nodes 117 and 118 thus convey alternating ramping voltages.
Level shifters 103 and 104 are utilized to shift the input voltage, nodes 117 or 118, by an adjustable DC value. This value is determined by the level shift control voltage on line 125. Comparator 105 outputs a true value when the ramping voltage on line 117 falls below the level shifted voltage signal 118 provided on line 120. Comparator 106 provides a true output value when ramping voltage signal 118 falls below level shifted voltage signal 117 provided on line 119.
Latch 107 is a set-reset flip-flop which conforms to the following truth table:
______________________________________ S R Q (n + 1) Q* (n + 1) ______________________________________ 0 0 Q (n) Q* (n) 0 1 0 1 1 0 1 0 1 1 -- -- ______________________________________
where 0 represents a logical false value, and 1 represents a logical true value. As shown by the truth table, a change of state only occurs if the S(set) input is asserted while the Q output is low, or if the R(reset) input is asserted while the Q output is high. The Q and Q* outputs of the set reset flip-flop are the oscillating outputs of the system, labeled F.sub.OUT.
The half cycle of the VCO core circuit is C.DELTA.V/I, where C is the capacitance of capacitor 114, .DELTA.V is the voltage difference between the maximum voltage of signals 117 and 118 and the threshold voltage provided by their level shifted counterpart as seen by the comparators, and I is the control current 130. The ideal VCO transfer function is: ##EQU3## where FOUT is the frequency of oscillating outputs 115 and 116. However, due to the inherent delay of the comparator and latch, the actual half cycle of the VCO is: EQU T.sub.H =C.DELTA.V/I+delv (equation 5)
where delv is the delay of the comparators and latch. Thus, the actual VCO transfer function is: ##EQU4## The delay of the comparators and latch in the VCO causes a non-linearity in the transfer function which becomes significant as frequencies approach the point where the term C.DELTA.V/I is on the same order of magnitude as delv.
A VCO of this form without the compensation loop, considering a one micron CMOS process, may operate linearly only up to about 20 MHz. The one sigma center frequency distribution may be larger than 4 MHz and temperature distortion may be higher than one percent per degree Celsius. A limited frequency range and the variation in the characteristics are unacceptable for almost all applications. For these reasons, a linearizing compensation loop is needed. The primary purpose of the compensation loop is to decrease the half cycle of the VCO core to compensate for the delay term at higher frequencies.
In the prior art FIG. 3, the compensation scheme centers around a frequency-to-voltage converter. The frequency-to-voltage converter is used to generate the effective trip-point voltage for the comparators. The frequency-to-voltage converter uses a six-phased clock running at one-quarter the VCO frequency. The output voltage of the frequency-to-voltage converter is then integrated and compared with a preset reference voltage to generate a compensated level shift control voltage.
In the compensation loop of FIG. 3, block 108 receives oscillating outputs 115 and 116 and supplies clock generator 109 with clock signals at one-quarter of the output oscillating frequency. Clock generator 109 provides clock signals of six different phases to frequency-to-voltage converter 110.
The frequency-to-voltage converter utilizes current signal 113, which is proportional to control current 130, to generate a voltage output which is related to the frequency input. The transfer function for the frequency-to-voltage converter is: EQU V.sub.F/V =[KIT'+(VPOS)C.sub.P ]/C' (equation 7)
where V.sub.F/V is the voltage output, K is the proportionality constant between signals 130 and 113, VPOS is the positive voltage supply value, C.sub.P is the parasitic capacitance within the frequency-to-voltage converter, and C' is the sum of C.sub.P and the charging capacitance, C.sub.F, within the frequency-to-voltage converter. T' is equal to the charging time within the converter, 1/F.sub.OUT +delf, where delf is a delay term for the inherent delay within the frequency-to-voltage converter caused by asymmetric switching times of the current switches in the converter, turn-on versus turn-off, rise-time versus fall-time, etc.
This converter works by integrating reference current 113, that is proportional to control current 130, onto a second capacitor that is ratioed to capacitor 114. The integration time is determined by the period of the VCO oscillating outputs 115 and 116.
The voltage integrated on the second capacitor is provided as output 126 to difference amplifier 111. The difference amplifier compares the output of the frequency-to-voltage converter with a reference voltage 124 and generates a level shift control voltage 125 for level shifters 103 and 104. The level shift control voltage provided by the difference amplifier 111 is: EQU V.sub.comp =Ref-(C.sub.F /C.sub.H)(V.sub.F/V -Ref) (equation 8)
where V.sub.comp is the compensated level shift control voltage, (C.sub.F /C.sub.H) is the gain of the difference amplifier, C.sub.H is the capacitance of capacitor 112, and Ref is the reference voltage. As the frequency of the oscillator rises, the output voltage of the frequency-to-voltage converter decreases and serves to decrease the level shift control voltage according to the above equation. As the level shift control voltage is decreased, the threshold voltages in the comparators are brought closer to the falling ramping voltage thus acting to decrease the half cycle of the VCO core. This serves to compensate for the delay time of the comparators and latch.
The time it takes for the VCO ramp to reach V.sub.comp is: EQU 1/F.sub.OUT -delv=(C.sub.V V.sub.comp)/I (equation 9)
Assuming for simplicity that K=1, C.sub.H &lt;&lt;C.sub.F, and C.sub.P &lt;&lt;C', an approximation for the compensated transfer function of the VCO is: EQU F.sub.OUT =I/(2{[Ref C.sub.F -C.sub.P VPOS]+I[(C.sub.H /C.sub.V)delv-delf]})(equation 10)
for the case where C.sub.V /C.sub.H&gt;&gt; 1. Equation 9 shows that the VCO delay term, delv, is reduced by the factor C.sub.H /C.sub.V. However, two new delay terms have been introduced by the compensation circuit. "delf" provides an uncompensated contributing factor to nonlinearity that becomes critical at frequencies where RefC.sub.F /I approaches delf, and "C.sub.P VPOS" causes a shift from the design goal in the voltage to frequency relationship and degenerates the PSRR due to its dependence on the power supply.